Method and device for updating a program

ABSTRACT

A method updating a program in a flash memory includes executing a first image of the program while an address space of the program is imaged onto the memory blocks, which are operated in a single-level mode; copying part of the first image from a range within the address space, which is imaged onto one of the blocks, into a backup block; setting the one of the blocks to a multi-level mode; while the address range is imaged onto the backup block, programming the one of the blocks with part of the second image besides for the part of the first image; switching the address range back to the block while the block remains in the multi-level mode; as long as the second image is incomplete, repeating the copying, programming, and switching with further parts of the second image; and subsequently executing the second image instead of the first image.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is the national stage of International Pat. App.No. PCT/EP2018/055466 filed Mar. 6, 2018, and claims priority under 35U.S.C. § 119 to DE 10 2017 205 274.0, filed in the Federal Republic ofGermany on Mar. 29, 2017, the content of each of which are incorporatedherein by reference in their entireties.

FIELD OF THE INVENTION

The present invention relates to a method for updating a program. Inaddition, the present invention relates to a corresponding device, acorresponding computer program, and a corresponding memory medium.

BACKGROUND

A non-volatile electronic memory component whose content is able to beelectrically erased is known to one skilled in the art as anelectrically erasable programmable read-only memory (EEPROM). Within thescope of the following statements, the term “EEPROM” is used in a broadsense of the word and in addition to conventional EEPROMs, alsoencompasses the more recent so-called flash memories, which are erasableblock by block. To allow for a non-volatile storage at a low energyconsumption, these flash EEPROM memories are predominantly used invehicle electronics according to the related art, where the informationstored in individual memory cells is stored in the form of electricalcharges on a floating gate or in a charge-trapping memory element of ametal insulator semiconductor field-effect transistor (MISFET). In thiscase, the memory cells are basically disposed as a matrix in what isknown as a cell array, and via a coordinate, the address lines are usedfor selecting a column or line of memory cells, and in the othercoordinate, data lines lead to the memory cells.

In an effort to increase the storage density, multi-level cells (MLC) inwhich more than one bit per line is stored are sometimes used in thiscontext. To make this possible, the charge quantity stored in a memorycell is dosed more finely and is also evaluated more precisely duringthe readout in order to be able to distinguish more than two possiblestates and to store more than one bit. In comparison with a single-levelcell (SLC), this has the disadvantage of a reduced read and write speed.An MLC also reacts with considerably greater sensitivity to possiblecharge losses.

In DE 102014223035 A1, a method is introduced for transmitting datawithin a computer system between a memory interface of a volatilememory, a memory interface, in particular an MLC-NAND memory, and aninterface of a microcontroller, the method including the reading in ofdata from the memory interface of the MLC-NAND memory at the start of abooting process of the microcontroller and the provision of the read-indata to the memory interface of the volatile memory.

SUMMARY

The present invention introduces a method for updating a program, acorresponding device, a corresponding computer program, and acorresponding memory medium.

The approach according to the present invention is based on therecognition that, due to the high cost of an update of the software (SW)of electronic vehicle systems requiring a workshop visit, the program orsystem images including the commands and data are increasingly modifiedover the air interface (over the air, OTA). There are differentpossibilities for executing such an update, but each of them hasdifferent advantages and disadvantages.

One conventional method is based on holding two system images inreadiness. In the case of an engine control, for example, the engineoperation is maintained using one system image, while a new system imageis installed on the respective control unit (electronic control unitECU). During the next start of the engine, the control unit is able tobe operated on the basis of the new system image.

In order to support this conventional method, twice as much memory spaceas in a control unit without an OTA capability is required since bothsystem images must be accommodated in the non-volatile memory (NVM) atthe same time. This has the disadvantage of high unit costs during theproduction of corresponding control units, regardless of whether thevehicle manufacturer or the original equipment manufacturer (OEM)ultimately utilizes their OTA-capability.

It is therefore provided to use memory cells as MLCs, i.e., at least ina two-level form, for the duration of the storing of two system imagesfor updating purposes. One advantage of this method is its reducedmemory cell requirement in comparison with conventional methods.Instead, only a fraction of the additional memory capacity is requiredby utilizing the MLC technology.

According to an example embodiment of the present invention, a method isused within the scope of OTA updates in a vehicle control unit on thebasis of a microcontroller (μC). In this way, a decision is able to bemade in the application as to whether to use a μC offering more flashmemory in the conventional manner, entailing a corresponding costdisadvantage, or to instead accept a reduced system performance in theinterim in order to have the two memory images available for an OTA inthe NVM.

Example embodiments of the present invention are illustrated in thefigures and discussed in greater detail in the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart that illustrates a method according to an exampleembodiment of the present invention.

FIG. 2 schematically represents a first step of the method according toan example embodiment of the present invention.

FIG. 3 schematically represents a second step of the method according toan example embodiment of the present invention.

FIG. 4 schematically represents a third step of the method according toan example embodiment of the present invention.

FIG. 5 schematically represents a fourth step of the method according toan example embodiment of the present invention.

FIG. 6 schematically represents a result of the method according to anexample embodiment of the present invention.

FIG. 7 schematically illustrates a control unit according to an exampleembodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 illustrates basic functional aspects of a method 10, which willnow be described in a synoptic view using one of FIGS. 2-6 in each case.In the latter figures, cells that are operated in the SLC mode areillustrated by a solid line, whereas cells operated in the MLC mode areshown by a dashed line.

FIG. 2 initially shows a normal operating state 11, in which a firstimage of the program is executed in a contiguous memory space 18 whilethe cells of all memory blocks are operated as SLCs, i.e., as singlelevel cells. An individual block can include 1 Mbyte in each case, and abackup block 19 of the same size, which is not necessarily encompassedby the address space 18 of the program and initially not yet utilizedfor the upcoming updating, is available for the upcoming update.

FIG. 3 illustrates the configuration following the request of a newimage. Here, the content of a block was copied to the backup block 19.The address range originally allocated to the original block is nowimaged onto the backup block 19 in hardware terms, which thus is quasi“superimposed” in the address space 18 of the program from the point ofview of the running program.

As illustrated in FIG. 4, the original block is now able to be switchedto the MLC mode and in addition to the first part, a part of a secondimage 17, which corresponds to the block size, is able to be programmed13. Since the block to be programmed is still quasi “exchanged” for thebackup block 19 in the address space 18 of the program, the functionalcapability of the first image is not adversely affected by thisprogramming operation.

Then, the MLC block is able to be superimposed again in the above senseat the original address 14 while remaining in the multi-level mode, sothat the first image can continue to be executed as in FIG. 5. A similarprocedure is used for further blocks, until all blocks are in the MLCmode and both images are therefore completely present in the NVM(decision 15—FIG. 1), which corresponds to the state 16 according toFIG. 6.

In this final state 16, the first or second image of the program canoptionally be executed. Once the functional capability of the secondimage 17 has been ensured—for instance in conjunction with differentcontrol units of a vehicle updated in this manner—the blocks can also besequentially reset to the single level mode according to the reversemethod in an effort to maximize the reliability of the program in acontinuous operation.

For example, this method 10 can be implemented in software or hardwareor in a mixed form of software and hardware, e.g., in a control unit 20,as illustrated by the schematic representation of FIG. 7.

1-12. (canceled)
 13. A method for updating a program in a memory, thememory including a plurality of blocks, the method comprising: executinga first image of the program while an address space of the program isimaged onto the blocks and the blocks are operated in a single levelmode; processing a second image of the program by executing a pluralityof iterations of a series of steps, wherein the iterations are executeduntil an entirety of the second image is processed and the steps of theiterations include: copying a part of the first image, which was formedfrom the imaging of an address range within the address space onto oneof the blocks, to a backup block of the memory; setting the one of theblocks to a multi-level mode; while the one of the blocks is set to themulti-level mode and the address range is temporarily imaged onto thebackup block, programming the one of the blocks with a respective partof the second image; and switching the address range back to the one ofthe blocks while the one of the blocks remains in the multi-level mode;and subsequent to the execution of the iterations of the processing ofthe entirety of the second image, executing the second image in place ofthe first image.
 14. The method of claim 13, further comprising:monitoring a functional capability of the second image during theexecution of the second image; and resetting the blocks to the singlelevel mode when the functional capability is determined in themonitoring to be ensured.
 15. The method of claim 13, furthercomprising: increasing an access time with which the memory is operatedto allow for an evaluation of information of the multi-level cells. 16.The method of claim 13, wherein: the control unit is operable in anormal single level cell (SLC) mode; and the control unit is operable ina multi-level cell (MLC) mode, in which an access time is longer, and aperformance is therefore lower, than when the control unit is operatedin the SLC mode.
 17. The method of claim 13, wherein the program, whenexecuted, causes control of a field device in a motor vehicle.
 18. Themethod of claim 17, wherein the second image is transmitted via an airinterface to the motor vehicle prior to the programming.
 19. The methodof claim 13, wherein the program, when executed, causes control of acombustion engine in a motor vehicle.
 20. The method of claim 13,wherein the memory is non-volatile.
 21. The method of claim 20, whereinthe memory is a flash EEPROM.
 22. The method of claim 21, wherein thememory is a NAND flash.
 23. The memory of claim 21, wherein the memoryis a NOR flash.
 24. A non-transitory computer-readable medium on whichare stored instructions that are executable by a processor and that,when executed by the processor, causes the processor to perform a methodfor updating a program in a memory, the memory including a plurality ofblocks, the method comprising: executing a first image of the programwhile an address space of the program is imaged onto the blocks and theblocks are operated in a single level mode; processing a second image ofthe program by executing a plurality of iterations of a series of steps,wherein the iterations are executed until an entirety of the secondimage is processed and the steps of the iterations include: copying apart of the first image, which was formed from the imaging of an addressrange within the address space onto one of the blocks, to a backup blockof the memory; setting the one of the blocks to a multi-level mode;while the one of the blocks is set to the multi-level mode and theaddress range is temporarily imaged onto the backup block, programmingthe one of the blocks with a respective part of the second image; andswitching the address range back to the one of the blocks while the oneof the blocks remains in the multi-level mode; and subsequent to theexecution of the iterations of the processing of the entirety of thesecond image, executing the second image in place of the first image.25. A device comprising a processor, wherein the processor is configuredto perform a method for updating a program in a memory, the memoryincluding a plurality of blocks, the method comprising: executing afirst image of the program while an address space of the program isimaged onto the blocks and the blocks are operated in a single levelmode; processing a second image of the program by executing a pluralityof iterations of a series of steps, wherein the iterations are executeduntil an entirety of the second image is processed and the steps of theiterations include: copying a part of the first image, which was formedfrom the imaging of an address range within the address space onto oneof the blocks, to a backup block of the memory; setting the one of theblocks to a multi-level mode; while the one of the blocks is set to themulti-level mode and the address range is temporarily imaged onto thebackup block, programming the one of the blocks with a respective partof the second image; and switching the address range back to the one ofthe blocks while the one of the blocks remains in the multi-level mode;and subsequent to the execution of the iterations of the processing ofthe entirety of the second image, executing the second image in place ofthe first image.
 26. The device of claim 25, wherein the device is amicrocontroller.